Field of the Invention
The invention relates to an operating method for an integrated memory having writeable memory cells and also to a corresponding integrated memory.
Known integrated memories having writeable memory cells are, for example, dynamic random access memories (DRAMs) and FRAMs or FeRAMs (Ferroelectric RAMs). These two types of memories in each case have memory cells with at least one storage capacitor, which serves for storing data. Memory cells of the one-transistor/one-capacitor type are generally customary in the case of DRAMs. Memory cells of FRAMs may likewise be of the one-transistor/one-capacitor type. They differ from the memory cells of a DRAM in that their storage capacitor has a ferroelectric dielectric. Different logic states of a datum to be stored can be distinguished by a different polarization of the ferroelectric dielectric, since the capacitance of the capacitor changes with its polarization.
U.S. Pat. No. 5,592,410 describes an FRAM having memory cells of the two-transistor/two-capacitor type. In this memory, too, the two storage capacitors of each memory cell have a ferroelectric dielectric.
It is accordingly an object of the invention to provide an operating method for an integrated memory having writeable memory cells and a corresponding integrated memory, which ascertains whether a functional disturbance occurred during a previous operation of the memory.
With the foregoing and other objects in view there is provided, in accordance with the invention, an operating method for an integrated memory having a writeable security memory cell for storing a security information item, word lines, bit lines crossing over the word lines, and writeable memory cells for storing data and disposed at crossover points between the word lines and the bit lines. The method includes performing the below described steps in an event of a write/read access. The security information item stored in the writeable security memory cell is read out before performing a write/read access to a respective memory cell of the writeable memory cells. An error signal is generated if the security information item read out has a first logic state. An access to the respective memory cell is carried out if the security information item read out has a second logic state. A write access to the writeable security memory cell is performed, in which a new security information item to be stored, which has the second logic state, is fed to the writeable security memory cell.
According to the invention, the integrated memory has the security memory cell which is likewise read in the event of an access to one of the normal memory cells. If the reading-out of the security information item stored in the security memory cell reveals that the logic state of the security information item does not correspond to that logic state with which the security information item should previously have been written to the security memory cell, a corresponding error signal is generated. The error signal then indicates that the storage of the security information item with a known second logic state did not take place correctly. Since the functional disturbance of the memory could also have affected the storage of the datum currently to be read out from the memory cell, the error signal is suitable as a corresponding warning to the operator of the integrated memory.
If no functional disturbance of the memory is detected during the reading of the security memory cell, in other words if the security information item has the second logic state, a new security information item to be stored, having the second logic state, is fed to the security memory cell. Provided that a functional disturbance does not occur in the process, the security information item is written correctly with the second logic state to the security memory cell. On the other hand, if a functional disturbance does occur, the security information item written in does not have the second logic state, but rather the first. If the operating method according to the invention is then carried out again at a later point in time, the functional disturbance will be detected, as already described above, and the error signal generated.
The method described can be carried out during any memory cell access. In order, however, to minimize the time required for carrying out the operating method according to the invention, it is expedient for the method only to be carried out each time the memory is initialized. It is then carried out, for example, only during the first reading-out from one of the memory cells. It can thus be ascertained whether a functional disturbance occurred during the operation of the memory that was effected before the initialization of the memory.
It is favorable if the security memory cell and the memory cells of the memory have the same construction. It is then ensured that functional disturbances of the memory have the same effect both in the event of a write access to the security memory cell and in the event of a write access to one of the memory cells.
It is advantageous, moreover, if, after the security information item has been read from the security memory cell and before the new security information item has been written in, a datum of the first logic state is generated in the security memory cell. This ensures that, even in the case of a memory whose memory contents are not destroyed during reading, a datum of the second logic state is stored in the security memory cell only when the new security information item of the second logic state is written correctly.
With the foregoing and other objects in view there is further provided, in accordance with the invention, an integrated memory. The integrated memory contains writeable memory cells for storing data, a writeable security memory cell for storing a security information item, and a control unit controlling accesses to the writeable memory cells and the writeable security memory cell for reading out the security information item stored in the writeable security memory cell if a write/read access is to be made to one of the writeable memory cells. A checking unit is provided for checking the security information item read from the writeable security memory cell and for generating an error signal if the security information item read out has a first logic state. The checking unit is connected to the control unit. The control unit serves for carrying out a write access to the writeable security memory cell, which follows the reading-out of the security information item and during which the control unit feeds to the writeable security memory cell a new security information item to be stored, having a second logic state, if no error signal was previously generated by the checking unit.
In this case, it is favorable if the security memory cell is already configured in such a way that its memory content is destroyed in the event of a read access, with the result that it contains a datum of the first logic state after the read access, irrespective of the previously stored datum. This automatically has the effect that a datum of the first logic state is stored in the security memory cell after the read access. Thus, such a datum does not have to be specially fed to the security memory cell in this case. All memories in which destructive reading takes place, such as, e.g. DRAMs and FRAMS, are suitable for this purpose.
In accordance with a concomitant feature of the invention, the writeable security memory cell is a ferroelectric memory cell. In addition, the writeable security memory cell and the writeable memory cells are identical.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an operating method for an integrated memory having writeable memory cells and a corresponding integrated memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.